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19-4569; Rev 0; 4/09
VGA Port Protector
General Description
The MAX4895E integrates level-translating buffers and features R, G, B port protection for VGA signals. The MAX4895E has H, V (horizontal, vertical) translating buffers that take low-level CMOS inputs from the graphics outputs to meet full +5.0V, TTL-compatible outputs. Each output can drive 10mA and meet the VESA(R) specification. In addition, the device takes the +5.0V, direct digital control (DDC) signals and translates them to the lower level required by the graphics device. This level is set by the user by connecting VL to the graphics output supply. The R, G, B terminals protect the graphics output pins against electrostatic discharge (ESD) events. All seven outputs have high-level ESD protection. The MAX4895E is specified over the extended -40C to +85C temperature range, and is available in a 16-pin, 3mm x 3mm TQFN package. 15kV--Human Body Model 8kV--IEC 61000-4-2, Contact Discharge Low Quiescent Current, IQ 5A (max) Low 3pF (max) Capacitance (R, G, B Ports) DDC Level-Shifting Protection and Isolation Horizontal Sync, Vertical Sync Level Shifting/ Buffering Input Compatible with VL Output Full +5.0V TTL Compatible (per VESA) 10mA Drive on Each H, V Terminal Space-Saving, Lead-Free, 16-Pin (3mm x 3mm) TQFN Package
Features
ESD Protection on H1, V1, SDA1, SCL1, R, G, and B
MAX4895E
Applications
Notebook Computers Desktops Servers Graphics Cards
Ordering Information
PART MAX4895EETE+ TEMP RANGE -40C to +85C PINPACKAGE 16 TQFN-EP* TOP MARK AHEEAA
VESA is a registered trademark of Video Electronics Standards Association Corporation.
+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
Typical Operating Circuit
TOP VIEW
H1
+3.3V +5V
Pin Configuration
SCL1 10 SCL0 9 8 7 SDA1 SDA0 N.C. VL 6 *EP 2 G 3 B 4 GND 5 H0 11
12
1F 1F
V0 13
VL EN VGA OUTPUTS 2 2 H0, V0 MAX4895E H1, V1 2 2 VGA PORT VCC
V1 14
SDA1, SCL1
SDA0, SCL0 R G B GND
VCC 15 EN 16
MAX4895E +
1 R
N.C.
TQFN (3mm x 3mm)
*CONNECT EXPOSED PAD TO GND.
________________________________________________________________ Maxim Integrated Products
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For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
VGA Port Protector MAX4895E
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.) VCC ........................................................................-0.3V to +6.0V VL .............................................................-0.3V to +(VCC + 0.3V) R, G, B, H1, V1, SCL1, SDA1...................-0.3V to +(VCC + 0.3V) EN, H0, V0, SCL0, SDA0 ............................-0.3V to +(VL + 0.3V) Continuous Current through SDA_, SCL_.........................30mA Continuous Short-Circuit Current H1, V1..........................20mA Continuous Power Dissipation (TA = +70C) for multilayer board: 16-Pin TQFN (derate 20.8mW/C above +70C) .......1667mW Junction-to-Case Thermal Resistance (JC) (Note 1) ......7C/W Junction-to-Ambient Thermal Resistance (JA) (Note 1) ........................................................................48C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +4.5V to +5.5V, VL = +2.0V to VCC, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5.0V, VL = +3.3V, and TA = +25C.) (Note 2)
PARAMETER SUPPLY OPERATION Supply Voltage Logic Supply Voltage VCC Supply Current VL Supply Current RGB CHANNELS R, G, B Capacitance R, G, B Leakage H_, V_, EN CHANNELS Input Threshold Low Input Threshold High Input Hysteresis Input Leakage Current Output-Voltage Low Output-Voltage High Propagation Delay Enable Time SDA_, SCL_ (DDC) CHANNELS On-Resistance, SDA, SCL Leakage Current, SDA, SCL R ON ILEAK VCC = +5.5V, I SDA SCL = 10mA, VSDA, SCL = +0.5V VL = 0 -1 20 55 +1 A VIL VIH VHYST ILEAK VOL VOH t PD t ON, t OFF VL = +3.3V, VCC = +5.5V I OUT = 10mA sink, VCC = +4.5V I OUT = 10mA source, VCC = +4.5V RL = 2.2k , CL = 10pF, VOL = +0.8V, VOH = +2.4V 2.4 15 15 -1 VL = +3.0V VL = +3.6V 2.0 100 +1 0.8 0.8 V V mV A V V ns ns C OUT f = 1MHz, VR,G,B = 1V P-P (Note 3) VCC = +5.5V -1 2.2 +1 pF A VCC VL ICC IL VL VCC VH0, VV0 = 0, VEN = VL VH0, VV0 = 0, VEN = VL (no load) 4.5 2 3.3 0.5 0.5 5.5 5.5 5.0 5.0 V V A A SYMBOL CONDITIONS MIN TYP MAX UNITS
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VGA Port Protector
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +4.5V to +5.5V, VL = +2.0V to VCC, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5.0V, VL = +3.3V, and TA = +25C.) (Note 2)
PARAMETER ESD PROTECTION SDA1, SCL1, H1, V1, R, G, B SDA1, SCL1, H1, V1, R, G, B Human Body Model (Note 4) IEC 61000-4-2 Contact 15 8 kV kV SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX4895E
Note 2: All devices are 100% production tested at TA = +25C. All temperature limits are guaranteed by design. Note 3: Guaranteed by design, not production tested. Note 4: Tested terminals to GND; 1F bypass capacitors on VCC and VL.
Typical Operating Characteristics
(VCC = +5.0V, VL = +3.3V, and TA = +25C, unless otherwise noted.)
HV BUFFER OUTPUT-VOLTAGE HIGH vs. TEMPERATURE
MAX4895E toc01
RON vs. VSDA0
60 SDA0, SCL0 ARE INTERCHANGEABLE 45 RON () VCL = +3.3V 30 TA = +85C TA = +25C 15 TA = -40C VCL = +5V TA = +85C TA = +25C TA = -40C 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VSDA0 (V) 4.0 -40 6.0
IOUT = 8mA 5.5
OUTPUT VOLTAGE (V)
5.0
4.5
-15
10
35
60
85
TEMPERATURE (C)
HV BUFFER OUTPUT-VOLTAGE LOW vs. TEMPERATURE
IOUT = 8mA 0.8 OUTPUT VOLTAGE (V)
MAX4895E toc03
1.0
0.6
0.4
0.2
0 -40 -15 10 35 60 85 TEMPERATURE (C)
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MAX4895E toc02
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VGA Port Protector MAX4895E
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 -- NAME R G B GND VL N.C. SDA0 SDA1 SCL0 SCL1 H0 H1 V0 V1 VCC EN EP High-ESD Protection Diodes for RGB Signals High-ESD Protection Diodes for RGB Signals High-ESD Protection Diodes for RGB Signals Ground Supply Voltage, +2.0V to VCC. Bypass VL to GND with a 1F ceramic capacitor. No Connection. Leave unconnected. SDA I/O. SDA0 referenced to VL. SDA I/O. SDA1 referenced to VCC. SCL I/O. SCL0 referenced to VL. SCL I/O. SCL1 referenced to VCC. Horizontal Sync Input Horizontal Sync Output Vertical Sync Input Vertical Sync Output Power-Supply Voltage, +4.5V to +5.5V. Bypass VCC to GND with a 1F ceramic capacitor. Enable for H1 and V1 Outputs Exposed Pad. Connect EP to GND or leave unconnected. For enhanced thermal dissipation, connect EP to a copper area as large as possible. Do not use EP as a sole ground connection. FUNCTION
Applications Information
The MAX4895E provides the level shifting necessary to drive two standard VGA ports from a graphics controller as low as +2.2V. Internal buffers drive the HSYNC and VSYNC signals to VGA standard TTL levels. The DDC switch provides level shifting by clamping signals to a diode drop less than VL (see the Typical Operating Circuit). Connect VL to +3.3V for normal operation.
Detailed Description
The MAX4895E integrates level-translating buffers and features R, G, B port protection for VGA signals. Horizontal and vertical synchronization (H0/V0) inputs feature level-shifting buffers to support low-voltage CMOS or standard TTL-compatible graphics controllers. The device meets 10A VESA drive requirements. The MAX4895E also features I2C level shifting using two nMOS devices. All outputs maintain 15kV Human Body Model (HBM) and 8kV Contact Discharge per IEC 61000-4-2 on seven terminals (SDA1, SCL1, H1, V1, R, G, B). The R, G, B pads protect the digital-to-analog converter (DAC) and are simply placed in parallel with the R, G, B outputs for the DAC and VGA socket.
Power-Supply Decoupling
Bypass V CC and V L to ground with a 1F ceramic capacitor as close as possible to the device.
PCB Layout
High-speed switches such as the MAX4895E require proper PCB layout for optimum performance. Ensure that impedance-controlled PCB traces for high-speed signals are matched in length and are as short as possible. Connect the exposed pad to a solid ground plane.
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VGA Port Protector
Functional Diagram
MAX4895E
VL
VCC
SDA0 CLAMP 15kV
SDA1
SCL0 15kV
SCL1
H0 15kV
H1
EN
V0 15kV
V1
R 15kV G 15kV B 15kV
MAX4895E
GND
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VGA Port Protector MAX4895E
Horizontal/Vertical Sync Level Shifter
HSYNC/VSYNC are buffered to provide level shifting and drive capability to meet the VESA specification. Input logic levels (VIL, VIH) are connected to VL (see the Electrical Characteristics table). The level-shifted outputs (H1 and V1) are pulled low when EN is driven low (see Table 1). Logic-level output (VOL, VOH) are +5.0V TTL compatible.
RGB
There are three terminals for R, G, and B. The only function of these terminals is to provide high-level ESD protection to the RGB lines, while at the same time, keeping the capacitance on the RGB lines to a minimum. The R, G, B terminals are identical, and any of the three terminals can be used to protect red, green, or blue video signals.
Display Data Channel Switches
The MAX4895E incorporates two nMOS switches for I2C level shifting. The SDA, SCL terminals are voltage clamped to a diode drop less than the V L voltage. Voltage clamping provides protection and compatibility with SDA, SCL signals and low-voltage ASICs. Supply +2.5V to +3.3V on VL to provide voltage clamping for VESA I2C-compatible signals. The SDA, SCL switches are identical, and each switch can be used to route SDA or SCL signals.
ESD Protection
As with all Maxim devices, ESD-protection structures are incorporated on all terminals to protect against electrostatic discharges encountered during handling and assembly. Additionally, the MAX4895E is protected to 15kV on the RGB terminals and outputs H1, V1, SDA1, and SCL1 by the Human Body Model (HBM). For optimum ESD performance, bypass VCC to ground with a 1F ceramic capacitor. ESD protection can be tested in various ways. The R, G, B terminals and outputs H1, V1, SDA1, and SCL1 of the MAX4895E are characterized for protection to the following limits: * 15kV using the Human Body Model * 8kV IEC 61000-4-2 Contact Discharge
Table 1. HV Truth Table
EN 1 0 FUNCTION HSYNC/VSYNC level shifting enabled H1, V1 = 0
ESD Test Conditions
Table 2. DDC Truth Table
EN 1 0 FUNCTION SDA0 to SDA1 SCL0 to SCL1 SDA1, SCL1, high impedance
ESD performance depends on a variety of conditions. Contact Maxim for a reliability report documenting test setup, methodology, and results.
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VGA Port Protector
Human Body Model (HBM)
Figure 1a shows the Human Body Model, and Figure 1b shows the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest that is then discharged into the test device through a 1.5k resistor. The major difference between tests done using the Human Body Model and IEC 61000-4-2 is higher peak current in IEC 61000-4-2 because series resistance is lower in the IEC 61000-4-2 model. Hence, the ESD withstand voltage measured to IEC 61000-4-2 is generally lower than that measured using the Human Body Model. Figure 1c shows the IEC 61000-4-2 model, and Figure 1d shows the current waveform for IEC 61000-4-2 ESD Contact Discharge test.
MAX4895E
IEC 61000-4-2
The IEC 61000-4-2 standard covers ESD testing and performance of finished equipment. However, it does not specifically refer to integrated circuits. The MAX4895E assists in designing equipment to meet IEC 61000-4-2 without the need for additional ESD-protection components.
Chip Information
PROCESS: BiCMOS
RC 1M CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE
RD 1500 DISCHARGE RESISTANCE DEVICE UNDER TEST HIGHVOLTAGE DC SOURCE
RC 50M TO 100M CHARGE-CURRENTLIMIT RESISTOR
RD 330 DISCHARGE RESISTANCE DEVICE UNDER TEST
Cs 100pF
STORAGE CAPACITOR
Cs 150pF
STORAGE CAPACITOR
Figure 1a. Human Body ESD Test Model
Figure 1c. IEC 61000-4-2 ESD Test Model
IP 100% 90% AMPS 36.8% 10% 0 0 tRL TIME
Ir
PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE)
IPEAK
I 100% 90%
10% tDL CURRENT WAVEFORM tr = 0.7ns TO 1ns 30ns 60ns t
Figure 1b. Human Body Current Waveform
Figure 1d. IEC 61000-4-2 ESD Generator Current Waveform
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VGA Port Protector MAX4895E
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 16 TQFN-EP PACKAGE CODE T1633+4 DOCUMENT NO. 21-0136
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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